Responsibilities Define the overall architecture of LPU chips based on a static dataflow architecture, including compute array design and on-chip SRAM memory hierarchy planning, to address…
Responsibility Responsible for high-performance block implementation (RTL to GDSII). Perform block level floor planning, power grid implementation, APR placement, timing optimisation, CTS a…
Responsibilities • Lead RTL design and implementation for AI chip SoC and subsystems. • Own key modules such as AI accelerator control logic, DMA, NoC/interconnect, memory subsystem, die-to…
CANAAN CREATIVE GLOBAL PTE. LTD. is seeking a hands-on digital-physical design engineer in Singapore. You will implement high-performance blocks from RTL to GDSII, perform floor planning, p…
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