Job Responsibilities - Work with the front-end design team to completethe chip floorplan, clock architecture, and powerplan. - Responsible for backend/PD tasks from theNetlist to the GDSII,…
Job Responsibilities - Responsible for synthesis from RTL to gate-level netlist - Work with RTL design team to create and verify SDC - Work with PnR engineers to improve PPA of digital modu…
Full time1–3 yearsOn-siteSingapore
Market insight
4 800 $3 500 $ – 7 000 $
3 500 $7 000 $
Based on 75 354 offers with salary for this country
