THE ROLE: The role involves building UVM/SystemVerilog testbenches, running simulations, debugging timing and protocol issues, and evaluating signal integrity, jitter, BER, and eye diagrams…
THE PERSON: You will have strong written and verbal communication skills and a systematic approach to your job. A team player, you are used to delivering results in a fast-paced environment…
Full time3–6 yearsOn-siteSingapore
Market insight
4 800 $3 500 $ – 7 000 $
3 500 $7 000 $
Based on 76 948 offers with salary for this country
