Lead Research Engineer I, FOWLP integration, Adv Pkg, IME

The Advanced Packaging Department at the Institute of Microelectronics (IME) is seeking a passionate and skilled Lead Research Engineer to join our team. This role is pivotal in advancing fan-out wafer level package (FOWLP) integration flatform with fine pitch multi-layer RDL and micro bump interconnections to integrate heterogenous multi-chiplet integration on fan-out based ultra large 2.5D interposers for AI applications. The position provides an exciting opportunity to contribute to groundbreaking technologies and collaborate with a dynamic team of researchers and external stakeholders.

Job Responsibilites

• Process integration development for high density multi-chip fan-out wafer level packaging for various applications such as AI/ HPC, Co-package Optics, Power devices etc.
• Drive the development of new capabilities such as fine pitch RDL, micro bumping, multi-layer RDL, polymer damascene etc required for future FOWLP integration.
• Establish novel RDL-first and mold-first fan-out packaging integration flows to meet industry partners requirements for various applications.
• Plan short loops and work with process module team to develop various processes and materials evaluation for FOWLP.
• Work with industry partners and multidisciplinary team members to execute the projects/assigned tasks by resolving issues.
• Conduct engineering experiments for process characterization to drive quality and yield improvements.
• Coordinate and support engineering build using developed packaging processes and integration.
• Lead industry and internal capability development projects with manageable risks and mentor less experienced colleagues.
• Inspire and mentor young talent in semiconductor technology, contributing to workforce development in the field.
• Publish new findings and technological advancement in prestigious journals and overseas/local conferences.

Job Requirements

• Bachelors/Masters in Materials Science and Engineering, Mechanical or Chemical Engineering, Electronics, Electrical and Computer Engineering, or any engineering or science related field.
• 5 to 10 years of experience in any semiconductor devices fabrication process integration, and experience in wafer level bumping, RDL and fan-out wafer level package integration will be added advantage.
• Hands-on experience in semiconductor manufacturing processes such as lithography, plating, etching as well as RDL and bumping process integration.
• Knowledge of wafer level fabrication processes and advanced packaging technologies, methodologies, and reliability characterization is preferable, but not mandatory.
• Strong analytical and problem-solving skills. Proficiency in data analysis and interpretation and design of experiments.
• Excellent written and verbal communication abilities.
• Ability to work collaboratively in a research-oriented environment (OEMs, customers, and Internal stakeholders). Demonstrated ability to manage multiple tasks and projects simultaneously.
• Demonstrated expertise in heterogeneous integration, FOWLP technologies, and advanced packaging processes.

The above eligibility criteria are not exhaustive. A*STAR may include additional selection criteria based on its prevailing recruitment policies. These policies may be amended from time to time without notice. We regret that only shortlisted candidates will be notified.