PD Engineer

Skills & Technical Expertise Required:

Netlist to GDSII at block level, Subsystem Level and at Full chip.

Worked on multiple tapeouts on Netlist to GDSII

Hierarchical partitioning and budgeting of block-level subsystems.

Implementation of high performance (HP) cores, low power designs

Node experience upto 3nm,7nm, 10nm, 14nm, 28nm.

Timing Signoff in loop through STA and ECO cycle at block and at interface.

Block level floor planning, power planning and IR drop analysis.

Scan chain reordering / Scan Chain repartitioning

CTS expertise and clock tree constraints creation for meeting specifications

MMMC optimization at Block and Sub-System Level

Timing closure with Crosstalk and AOCV / POCV

TCL scripting to fundamentally understand tool usage.

Mandatory EDA Skills

PnR tools such as Synopsys ICC/ICC2 and/or Cadence Innovus