III-V Wafer Fab Process Engineer (Lithography)

Position Summary

The III-V Wafer Fab Process Engineer is responsible for developing, qualifying, and sustaining photolithography and etch processes used in the manufacture of III-V compound semiconductor devices, including InP and GaAs based technologies. The engineer will establish robust manufacturing processes for R&D, new product, optimize yield and process capability, support high-volume manufacturing, and collaborate with cross-functional teams to deliver reliable and cost-effective manufacturing solutions.

Key Responsibilities

Develop and optimize photolithography processes for III-V wafer fabrication.

• Establish process windows for critical lithography parameters, including:

1. Photoresist coating, bake and develop
2. Exposure dose and focus
3. Overlay accuracy
4. Critical dimension (CD) control
5. Pattern fidelity and defectivity
6. Qualify new photoresists, developers, bottom anti-reflective coatings (BARC), and lithography materials.
7. Develop processes for broadband, i-line, DUV (193 nm), aligner/stepper/scanner platforms.
8. Optimize lift-off lithography processes for metal patterning.
9. Minimize defects such as particles, bridging, resist lifting, and pattern collapse.
10. Mask Layout and reticle design / tape out

Process Qualification

• Develop qualification plans for new lithography and etch equipment.
• Define process acceptance criteria and process capability targets.
• Conduct Design of Experiments (DOE) to optimize process windows.
• Perform process characterization and statistical analysis.

Manufacturing Support

• Monitor process health using SPC.
• Investigate process excursions and implement corrective and preventive actions.
• Troubleshoot lithography and etch-related issues affecting yield or productivity.
• Support engineering lots, pilot production, and high-volume manufacturing.

Yield Improvement

• Analyze yield loss associated with lithography and etch processes.
• Perform root cause analysis using 8D, 5 Why, Fishbone, and FMEA methodologies.
• Drive continuous improvement projects to reduce defects and improve process capability.

Process Control & Documentation

• Develop and maintain: WI, Control Plans, PFMEA, OCAP, Process Recipes, ECO

Qualifications

• Bachelor's, Master's, or PhD in Electrical Engineering, Materials Science, Chemical Engineering, Physics, or Microelectronics.
• 5+ years of semiconductor wafer fabrication experience.
• Minimum 3 years of direct experience in lithography and/or plasma etch processes.
• Experience with III-V semiconductor manufacturing is highly preferred.