Junior/Senior Memory Design Engineer (SRAM) (Semiconductor)

Responsibilities

• Define memory architecture and carry out end-to-end circuit design for embedded SRAM IP across multiple process technologies, supporting memory types such as Single-Port (SP) SRAM, Dual-Port (DP) SRAM, Register Files, and ROM.
• Work closely with layout engineers and provide technical guidance for the physical implementation of SRAM memory arrays and peripheral analog circuitry.
• Contribute to the development, enhancement, and maintenance of SRAM Compiler solutions.
• Support the creation of SRAM IP Design Kits (DK), including deliverables such as Verilog models, Liberty files, datasheets, bitmaps, and related collateral.
• Assist in the design, development, and validation of SRAM-related test chips.

Requirements

• Bachelor's or Master's degree in Microelectronics or a related field
• Minimum of 3 years of hands-on experience in transistor-level analog and mixed-signal circuit design.
• Experience in memory design, including SRAM, ROM, and Register File architectures.
• Proficient in industry-standard analog EDA tools such as Cadence Virtuoso, Spectre, HSPICE, XA, FINESIM, and similar platforms for custom circuit design and simulation.
• Experience with SRAM chip testing and failure analysis is considered an advantage.
• Familiarity with advanced semiconductor technologies, including CMOS, FinFET, and FD-SOI, along with experience working across different process nodes.

Interested candidates who wish to apply for the advertised position, please click 'APPLY' to submit your application

EA License No: 13C6305

Reg. No.: R1874608 (Lee Jia Hou)

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