Research Fellow (Circuit Design for Carbon Nanotube FET Logic and Emerging Memory)

Interested applicants are invited to apply directly at the NUS Career Portal. Please note your application will only be processed if you apply via NUS Career Portal.

NUS Career Portal link - https://careers.nus.edu.sg/job/Research-Fellow-%28Circuit-Design-for-Carbon-Nanotube-FET-Logic-and-Emerging-Memory%29/34218-en_GB/

We regret that only shortlisted candidates will be notified.

Job Description

The Department of Electrical and Computer Engineering (ECE), College of Design and Engineering, is seeking a Research Fellow to lead the circuit design track of a research programme on nanoelectronic integrated circuits — carbon nanotube FET (CNFET) logic, emerging on-chip memories, and their monolithic 3D integration on silicon CMOS.
Key responsibilities:
• Design CNFET digital circuits and standard cells, and build and calibrate CNFET compact models (Verilog-A) against measured device data.
• Design memory macros in emerging memory technologies — including gain cell, oxide-semiconductor based and resistive (RRAM) memories — covering the array and its peripheral circuits (sense amplifiers, write drivers, decoders and drivers, timing and refresh control).
• Carry out device–circuit co-optimisation and variation-aware, defect-tolerant design for immature technologies, and benchmark power, performance and area against silicon CMOS.
• Explore monolithic 3D integration enabled by the low-temperature (BEOL-compatible) flows — memory over logic, and compute-in-memory / edge-AI applications.
• Produce test-vehicle layouts with DRC/LVS closure, coordinate tape-out with the process team and industry partners, and lead the electrical testing and analysis of fabricated chips.
• Publish in leading venues, supervise graduate students, and contribute to invention disclosures and research proposals.

Qualifications

Essential:
• PhD in Electrical Engineering, Microelectronics, Computer Engineering or a closely related field (awarded, or thesis submitted, at the time of application).
• Demonstrated digital and/or mixed-signal IC design experience using a commercial design flow (Cadence Virtuoso and Spectre, synthesis and place-and-route), including full-custom layout with DRC/LVS closure.
• Experience designing memory macros and their peripheral circuits — sense amplifiers, write drivers, decoders and timing control — for SRAM, DRAM, gain cell or emerging memory.
• Compact modelling and device–circuit co-design, including Verilog-A model development and parameter extraction from measured data.
• Statistical and Monte Carlo circuit analysis, and the ability to reason about variability and yield when the technology has no mature PDK.
• Scripting for design automation and data analysis (Python, TCL, SKILL or equivalent).
• A publication record commensurate with career stage, strong written and spoken English, and the ability to work independently and to guide junior researchers.
Desirable:
• Circuit design on an emerging device technology — CNFETs, 2D-material FETs, oxide-semiconductor (IGZO/ITO) FETs, RRAM, or ferroelectric devices.
• Monolithic 3D IC design, memory-over-logic partitioning, or thermal-aware physical design.
• Standard-cell library development and characterisation.
• Tape-out and silicon bring-up experience.
• Compute-in-memory accelerator design, or hardware for edge AI.
• Experience working alongside a foundry or an external process partner.