AI ASIC Memory Compiler, Technical Manager

Job Description

In the Memory Design Automation team, we work seamlessly with worldwide memory design teams to deliver high performance, low power and small area in-house memories design kits and design flows under advanced technology nodes. We are looking for candidate to join us as memory design automation engineer for the delivery of robust memory and development of Memory Compiler automation flow.

• Delivering robust memory solutions.
• Developing Memory Compiler automation flows.
• Creating behavioral, FPGA, timing, and DFT simulation models.
• Debugging andoptimizing SRAM models for ASIC design flows.
  

Job Requirements

• Knowledge of high performance, low power SRAM/ROM and VLSIdesign is an added advantage. Experience with EDA tools will be helpful.
• With min. 8 years of relevant experience in similar industry.
• Proficient with Perl, Shell, Python, C/C++ languages, knowledgewith AI machine learning algorithm and infrastructure is an added advantage.
• Good understanding of verilog syntax and its various aspects,such as behavioral, RTL and synthesizable verilog is a must.
• Good understanding of liberty timing syntax.
• Knowledge and experience with EDA simulation tools such as VCS,NC is required.
• Experience with EDA tools will be helpful:
• DFT: Logicvision, Tessent, Fastscan
• Synthesis: Design compiler, Genus
• Simulation tools:VCS, QuestaSim, NC
• STA tools such as PrimeTime

Interested candidates may apply through the application system. We regret to inform only Shortlisted candidates will be notified.

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