Job is active

Senior Digital Engineer

7 500 – 11 000 $

Location

TAI SENG STREET, 18 TAI SENG

Open in maps

About this job

What we’re looking for:

We are seeking a highly skilled Design Engineer to join our Silicon Engineering team. This role involves driving the design, implementation, and optimization of cutting-edge SoCs through advanced physical design methodologies. The ideal candidate will have deep expertise in synthesis, floorplanning, place-and-route, timing closure, power/performance optimization, and sign-off flows.

Skills you’ll need:

  • Execute the end-to-end physical design flow for complex SoCs and IP blocks (from RTL handoff to GDSII).
  • Define and drive floorplanning, clock-tree synthesis (CTS), placement, routing, and timing closure strategies.
  • Own and optimize power, performance, and area (PPA) metrics for assigned designs.
  • Manage design constraints, synthesis strategies, and sign-off criteria (timing, IR drop, EM, DRC/LVS).
  • Collaborate with front-end RTL, DFT, verification, and packaging teams to ensure seamless integration.
  • Drive EDA tool flow automation and methodology enhancements for improved efficiency and scalability.
  • Mentor and guide junior engineers, fostering technical growth and design excellence.
  • Work closely with foundries and vendors on process technology bring-up, PDK updates, and tape-out readiness.

Education and/or Experience:

  • Bachelor’s or Master’s degree in Electrical Engineering, VLSI, or related field.
  • 4+ years of experience in ASIC physical design
  • Hands-on expertise in EDA tools: Synopsys (ICC2, Fusion Compiler, PrimeTime),
  • Cadence (Innovus, Tempus), or equivalent.
  • Strong background in timing analysis, low-power methodologies, and ECO flows.
  • Solid understanding of architecture-to-GDSII flows and sign-off requirements.
  • Experience with chip-level integration and hierarchical design methodologies.
  • Knowledge of low-power design techniques (UPF/CPF, power gating, DVFS).
  • Familiarity with DFT, STA, and physical verification methodologies.
  • Exposure to multi-clock, multi-voltage, and multi-domain designs
  • Excellent problem-solving and communication skills.

Benefits & Perks:

Not only will you be joining a highly skilled and tight-knit team where every engineer makes a significant impact on the product; we also strive for good work/life balance and to make our environment welcoming and fun.

  • Medical and dental insurance coverage including spouse and child(ren)
  • Bi yearly health screening and flu vaccination
  • Office location is above Tai Seng MRT station

Market insight

61% above median
5 747 $

Based on 307 offers with salary for Jobs hybrid in Sengkang

Full salary breakdown

SILICON LABORATORIES INTERNATIONAL PTE. LTD. Sengkang ·

Digital Engineer II

5 000 – 8 300 $
Full time3–6 yearsHybridSengkang
SILICON LABORATORIES INTERNATIONAL PTE. LTD. Sengkang ·

Digital Engineer I

5 000 – 7 000 $
Full timeNo experienceHybridSengkang
SILICON LABORATORIES INTERNATIONAL PTE. LTD. Sengkang ·

Product Test Engineer

5 000 – 7 000 $
Full timeNo experienceHybridSengkang
SILICON LABORATORIES INTERNATIONAL PTE. LTD. Sengkang ·

Digital Engineer I

5 000 – 7 000 $
Full timeNo experienceHybridSengkang
KLA-TENCOR (SINGAPORE) PTE. LTD. Sengkang ·

Buyer/Planner

3 500 – 7 000 $
Full time1–3 yearsOn-siteSengkang

Frequently asked questions

What salary can I expect?

The employer lists 7 500 – 11 000 $ for this role at SILICON LABORATORIES INTERNATIONAL PTE. LTD. in Sengkang. For comparison, the local market median is about 5 747 $ based on 307 similar offers.

How do I apply for this job?

Open the original source page and contact the employer there. Finder never charges job seekers.

Are these jobs up to date?

Yes. Finder regularly refreshes vacancies from public sources and removes closed offers.

Where can I see employment type and work format?

Key conditions are shown above the description. You can also open related listings for SILICON LABORATORIES INTERNATIONAL PTE. LTD. and Sengkang.

Apply