Job is active
Digital Engineer II
5 000 – 8 300 $
About this job
- Execute the end-to-end physical design flow for complex SoCs and IP blocks (from RTL handoff to GDSII).
- Define and drive floorplanning, clock-tree synthesis (CTS), placement, routing, and timing closure strategies.
- Own and optimize power, performance, and area (PPA) metrics for assigned designs.
- Manage design constraints, synthesis strategies, and sign-off criteria (timing, IR drop, EM, DRC/LVS).
- Collaborate with front-end RTL, DFT, verification, and packaging teams to ensure seamless integration.
- Drive EDA tool flow automation and methodology enhancements for improved efficiency and scalability.
- Mentor and guide junior engineers, fostering technical growth and design excellence.
- Work closely with foundries and vendors on process technology bring-up, PDK updates, and tape-out readiness.
Market insight
16% above median5 747 $
5 747 $5 747 $
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The employer lists 5 000 – 8 300 $ for this role at SILICON LABORATORIES INTERNATIONAL PTE. LTD. in Sengkang. For comparison, the local market median is about 5 747 $ based on 307 similar offers.
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