Junior/Senior IP DK design Engineer (Semiconductor)

Responsibilities

• Take ownership of library characterization activities for Memory IP and other IP products, while driving improvements in characterization flow automation.
• Generate and maintain Design Kits (DK) for Memory IP and other IPs, including deliverables such as Liberty (.lib), CDL, IBIS, Verilog, LEF, and related files.
• Conduct pre-QA verification for Memory IP to ensure functional correctness, performance accuracy, and compatibility across a range of EDA tools.

Requirements

• Bachelor's or Master's degree in Microelectronics or a related field
• At least 3 years of hands-on experience in IC design, IP development, or Design Kit (DK) generation.
• Strong understanding of Liberty format and syntax, including timing, constraint, and power modeling concepts. Familiarity with timing, power, and noise models such as NLDM, CCS, LVF, and OCV is required.
• Knowledge of library characterization methodologies, with proficiency in characterization tools such as Liberate, Liberate MX, or SiliconSmart.
• Solid understanding of SPICE simulation and the ability to independently develop, debug, and validate SPICE testbenches.
• Familiarity with the ASIC design flow and experience using EDA tools for synthesis, static timing analysis (STA), place-and-route (P&R), and power analysis.
• Proficient in scripting and automation using languages such as Perl, Python, Tcl, and Skill.

Interested candidates who wish to apply for the advertised position, please click 'APPLY' to submit your application

EA License No: 13C6305

Reg. No.: R1874608 (Lee Jia Hou)

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